Embedded Systems and Power Electronics

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I am currently a PhD student at UC Berkeley, following a 6-year journey working at Apple after my undergrad years at Cornell University. I am a 2025 Paul & Daisy Soros fellow. I grew up in Dhaka, Bangladesh where my interest in electronics was cultivated, resulting in the creation of this blog.

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Showing posts with label buck. Show all posts
Showing posts with label buck. Show all posts

Aug 5, 2025

Why is my buck output ripple higher than expected: ceramic capacitor derating vs voltage


Fig. 0a - The test hardware comprising a buck converter operating at 50kHz and 50% duty cycle. The PWM signals are generated from an on-board RP2040. The buck inductor (not shown) is soldered on the reverse side of the PCB.
Fig. 0b - Back side of the test PCB, where the input electrolytic caps and output inductor are soldered.



Fig. 1 - Buck converter

In a typical buck converter shown in Fig. 1, the output ripple voltage is an important design specification. Sensitive loads may specify a maximum ripple voltage. The max allowable voltage for the load is also limited by the ripple, especially for loads with tight specifications such as many processors.

The output ripple voltage is given by

\[ \Delta V_\mathrm{out} = \frac{V_\mathrm{in}D(1-D)}{8LCf_\mathrm{sw}^2} \]

The derivation is given at the end of this post for those interested. The different parameters are:

  • \( \Delta V_\mathrm{out} \) = peak-to-peak output ripple voltage
  • \( V_\mathrm{in} \) = input voltage
  • \( D \) = duty cycle
  • \( L \) = inductance
  • \( C \) = output capacitance
  • \( f_\mathrm{sw} \) = switching frequency

We can look at the output ripple using the power testbench. The converter is run at 50kHz and 50% duty cycle, with varying input voltages. The output capacitor of the converter is the parallel combination of 4x 0805 10µF caps (GRM21BR61H106KE43) and 1x 1206 10µF cap (CGA5L3X5R1H106K160AB). The inductor is rated at 5.6µH, specifically the Wurth 732-3799-1-ND.

Based on this, you would expect the output ripple at 10V input to be given by:

\[ \Delta V_\mathrm{out} = \frac{V_\mathrm{in}D(1-D)}{8LCf_\mathrm{sw}^2} = \frac{10V \cdot 0.5 \cdot 0.5}{8\cdot 5.6\mu H \cdot 50\mu F \cdot (50\;kHz)^2} =0.45\;V \]

The ripple waveform is obtained with a scope that is AC coupled and can be seen below in Fig. 2. From the scope shot, it appears that the voltage ripple is about 0.75V, which is a fair bit higher than the expected ripple. So what gives?

Fig. 2 - Output ripple, AC coupled, 500mV/division, Vin=10V, Vout=5V

The culprit here is voltage derating of ceramic capacitors. Much like how I've previously written about electrolytic capacitors derating with frequency, ceramic capacitors (particularly class II dielectrics) can derate substantially with voltage. This has to do with the reduced permittivity of the dielectric, reducing the capacitors' ability to store energy at higher voltage biases. This is often given in manufacturer technical documentation. For our caps, the derating charts are reproduced below.

Fig. 3a - GRM21BR61H106KE43 DC bias characteristics, credit: Murata

Fig. 3b - GRM21BR61H106KE43 5V DC bias corresponds to a 6.4µF capacitance

Fig. 4a - CGA5L3X5R1H106K160AB DC bias characteristics, credit: TDK

Fig. 4b - CGA5L3X5R1H106K160AB 5V DC bias corresponds to a 9.1µF capacitance; you will often notice that larger packages correspond to reduced derating and hence have larger capacitances for the same initial capacitance and voltage rating

Considering the derating from Figs. 3-4, the total output capacitance is 34µF. With this new value plugged in, the expected output ripple is about 

\[ \Delta V_\mathrm{out} = \frac{V_\mathrm{in}D(1-D)}{8LCf_\mathrm{sw}^2} = \frac{10V \cdot 0.5 \cdot 0.5}{8\cdot 5.6\mu H \cdot 34.7\mu F \cdot (50\;kHz)^2} =0.64\;V \]

This is much closer to the observed value with a 14.5% error, something that is fairly within the tolerance of different components.

If we now look at the results with 20V input (corresponding to 10V output), we would expect an output ripple of double that for the 10V input, corresponding to 1.3V; if the caps didn't further derate. However, we can find again from the manufacturer data that the total output capacitance is 19.7µF, down from 34µF, which would correspond to a greater increase in the ripple. This is shown in Figs. 5a and 5b.

Fig. 5a - GRM21BR61H106KE43 10V DC bias corresponds to a 3.2µF capacitance

Fig. 5b - CGA5L3X5R1H106K160AB 10V DC bias corresponds to a 6.9µF capacitance

Fig. 6 - Output ripple, AC coupled, 500mV/division, Vin=20V, Vout=10V

The output ripple observed with 20V input is shown in Fig. 6. The measured ripple corresponds to 2.7V, which further highlights the substantial capacitance drop with 10V bias for the output ceramic capacitors!

The expected ripple with ideal caps is given by
\[ \Delta V_\mathrm{out} = \frac{V_\mathrm{in}D(1-D)}{8LCf_\mathrm{sw}^2} = \frac{20V \cdot 0.5 \cdot 0.5}{8\cdot 5.6\mu H \cdot 50\mu F \cdot (50\;kHz)^2} = 0.9\;V \]

However, with derated capacitance, the expected ripple is 

\[ \Delta V_\mathrm{out} = \frac{V_\mathrm{in}D(1-D)}{8LCf_\mathrm{sw}^2} = \frac{20V \cdot 0.5 \cdot 0.5}{8\cdot 5.6\mu H \cdot 19.7\mu F \cdot (50\;kHz)^2} = 2.3\;V \]
This is much closer to the observed ripple value.

For proper filtering, it is crucial to consider the DC bias impact on the ceramic capacitors and the corresponding derating, in addition to component tolerance! Otherwise, the filtering will be insufficient and the ripple will be much higher than expected, as shown here. This could result in poor circuit performance or even component damage!

Note that the circuit parameters here were chosen to have large output ripple to illustrate the concern described in this article. In almost any application, this circuit has a very high ripple percentage. Even with the components as present, the frequency can be increased substantially to reduce the ripple. Alternately, the output inductor or capacitance can be increased.

Ripple Derivation

Fig. D1 - Buck Converter


Fig. D2 - Buck Converter when QH is on


Fig. D3 - Buck Converter when QL is on

To find the output ripple in a buck converter, we start from the inductor current, which can be determined from the inductor voltage in either QH on or QL on state. We can identify that \( i_\mathrm{L} \) increases when QH is on since \( v_\mathrm{L} \) is positive then. And similarly, \( i_\mathrm{L} \) decreases when QL is on since \( v_\mathrm{L} \) is negative.

QH is on for a fraction of the switching period given by the duty cycle D. For a buck converter, the output voltage is given by \( V_\mathrm{out} = D V_\mathrm{in} \). The inductor voltage relationship \( v_\mathrm{L} = L \frac{di_\mathrm{L}}{dt} \) can be rewritten for constant voltage \( v_\mathrm{L} = L \frac{\Delta i_\mathrm{L}}{\Delta t} = L \frac{\Delta i_\mathrm{L}}{D T_\mathrm{sw}} \) where \(T_\mathrm{sw}\) is the switching period.

The peak-to-peak inductor current ripple is thus given by
\[ \Delta i_\mathrm{L,pp} =  \frac{V_\mathrm{in}-V_\mathrm{out}}{L}\cdot \frac{D}{f_\mathrm{sw}} = \frac{V_\mathrm{in}(1-D)D}{Lf_\mathrm{sw}} \]
We know from Fig. D1 that \( i_\mathrm{L} = i_\mathrm{C} + i_\mathrm{out} \). We can find the impedance of the output capacitor and determine the current split between it and the output load. We can assume (and confirm mathematically) that the impedance of the output cap at high frequencies (such as in a typical buck converter) is much lower than the load resistance. Thus, we can assume that the inductor ripple current is going through the output cap, as shown in Fig. D4, and that the DC amount is going through the load resistor.
Fig. D4 - Current going through the output capacitor

When the ripple current is positive (for half of \( T_\mathrm{sw} \) ), the output capacitor is charged and when the ripple current is negative, the output capacitor is discharged. The peak-to-peak capacitor voltage ripple can be found from the positive inductor current charging the cap, where Q is the charge \( \int i_\mathrm{C}\;dt = \frac{1}{2} \frac{\Delta i_\mathrm{L,pp}}{2} \frac{T_\mathrm{sw}}{2} = \frac{1}{8} \Delta \frac{i_\mathrm{L,pp}}{f_\mathrm{sw}} \)

\[  \Delta V_\mathrm{out} = \frac{Q}{C} = \frac{1}{8Cf_\mathrm{sw}} \Delta {i_\mathrm{L,pp}} = \frac{1}{8Cf_\mathrm{sw}} \frac{V_\mathrm{in}(1-D)D}{Lf_\mathrm{sw}} = \boxed{ \frac{V_\mathrm{in}D(1-D)}{8LCf_\mathrm{sw}^2} } \]

As a final check, we can go back to checking the magnitude of the output capacitance compared to the load resistance (10Ω output resistor was used) with the circuit in Fig. 0.
\[ |Z_\mathrm{C}| = \frac{1}{2 \pi f_\mathrm{sw} C} = \frac{1}{2 \pi 50\;kHz \; 19.7\mu F} = 0.16 \Omega \ll 10 \Omega \] 

Mar 30, 2025

Power Testbench and Upcoming Power Electronics Tutorials


While I have written many articles on this blog about power electronics related topics, I am hoping to share more fundamentally structured tutorials and articles, based on power electronics fundamentals that have been reinforced during my time in graduate school. To that end, I have designed a testbench to cover topics ranging from basics to slightly more involved ones. I have completed the design of a power electronics test bench, sent out the PCB files to be fabbed at OSHPark, and ordered parts from Digikey.

Here are some ideas I have for topics to cover, and I'd love to get feedback on other topics of interest!

Here are a couple 3D renders of the testbench hardware from Altium:

Top side render

Bottom side render

I will go over more details of the design and will be sharing the Altium design files and bringup progress when the board is back! I am hoping to use this design and framework to provide more structured tutorials on power electronics, building on past articles on this blog.

Jul 3, 2024

Generating complementary PWM with adjustable deadtime for the RP2040


I have previously discussed the benefits of using the Raspberry Pi Pico, leveraging the easy-to-program Micropython along with the capable hardware peripherals: 2023 Updates: PhD; Pi Pico and Quick and dirty PIC16F72 programmer with the Pico

Several articles in the blog have previously described applications of PWM in embedded systems, such as Stereo audio player using the PIC32, MCP4822, microSD card and the MDDFS libraryDC motor control with PIC16F877A - Practical example of PIC PWM and Generation of sine wave using SPWM in PIC16F684.

Complementary PWM signals with 500ns deadtime

The underlying RP2040 in the Pi Pico provides an easy-to-use and still powerful and flexible set of PWM peripherals that can enable a wide range of applications. A common requirement in power electronics is the generation of complementary PWM signals. For example, the complementary PWM signals are used in a synchronous buck converter, shown below, to drive the switches S1 and S2.

Synchronous Buck Converter
Image source: https://commons.wikimedia.org/wiki/File:300px-Synch_buck.PNG

To prevent shoot-through, a deadtime is employed. Shoot-through is the event when both S1 and S2 are turned on, causing a large current through them due to shorting across the supply voltage. Even if the generated PWM signals are non-overlapping (ie S1 and S2 are never turned on together), delays in the circuitry - through the gate drivers and the power switches themselves - can still result in shoot-through conditions. In a severe case, the shoot-through can cause damage to the switches, blowing them out. In a more moderate case, small overlap times can result in reduced efficiency due to wasted power, but not necessarily damage to the switches. To combat this issue, a deadtime is inserted between the S1 and S2 driving signals. This is an amount of time when both switch control signals are zero allowing for system transients to settle out. How large it should be depends on the circuit parameters and behavior.

In many cases, gate drivers can have built-in features to insert dead-times, such as the LM5106. However, the ability to generate this in the microcontroller itself gives greater flexibility in the selection of gate driver. Further, it allows tuning the time easily in software rather than needing to change hardware components to change deadtimes.

Fortunately, the Pi Pico makes it fairly straightforward to do this!

The details of the PWM peripheral are outlined in the RP2040 datasheet section 4.5. You can find the code sample here: https://github.com/SyedTahmidMahbub/comppwm_rp2040

The corresponding source code is copied below for convenience:


The RP2040 has 8x PWM slices, each with 2 channels. The complementary PWM waveforms are produced on these 2 channels (A and B) on a given slice. The slice to GPIO mapping is shown below.
PWM slice+channel mapping to GPIO pins
Image source: RP2040 datasheet section 4.5.2

The key aspects of the code are:
  • Use Micropython to init PWM for the associated GPIO pins (A and B).
  • Alter RP2040 registers to configure for complementary PWM. This consists of two settings being changed.
    • Invert channel B relative to channel A.
    • Use center-aligned (phase-correct) PWM instead of edge-aligned. This ensures that the deadtime is applied to both rising and falling edges of channel A. If edge-aligned PWM was used, the channels would be set high together and the deadtime would only be applied on the falling edge of channel A.
  • The deadtime is applied to channel B such that channel A's duty cycle corresponds to the desired/set duty cycle.
  • The duty cycles corresponding to both channels A and B are updated with one register write.
  • The frequency of the output PWM using center-aligned/phase-correct mode is half that when using the default edge-aligned mode.
An example of phase-correct/center-aligned PWM operation is shown in the figure below, taken from the RP2040 datasheet.

Image source: RP2040 datasheet section 4.5.2.1

To generate the complementary signal on channel B, the duty cycle is computed as the sum of the pulse count corresponding to the desired duty cycle and the desired deadtime ticks. With a 125MHz clock for the RP2040 and default clock/divider settings, this corresponds to 8ns per tick. The inversion of channel B then ensures the production of the desired complementary setting.

Shown below are waveforms for GP16 (PWM 0A) and GP17 (PWM0B) for 100kHz PWM, 25% duty cycle and a 504ns deadtime. The deadtime can be verified by recognizing that it corresponds to one horizontal division, which is set to 500ns.

Complementary PWM signals with 500ns deadtime

Taking a zoomed out view of the waveform highlights the 100kHz frequency and illustrates the complementary PWM generation over multiple cycles, as shown below.

3 cycles of 100kHz PWM complementary signals

A natural use case for this generated complementary PWM signal is to control a synchronous buck converter to achieve high efficiency step down operation. Since Micropython will limit the design of a fast control loop, applications where the high frequency PWM is coupled with a low-bandwidth controller make for a natural home for this use case. A solar MPPT battery charger would make for an ideal usage scenario. Alternately, if the same configuration technique is applied in C, fast control loops can then be designed and implemented.