A low-cost high-side current sense amplifier: design considering non-idealities

A low-cost high-side current sense amplifier: design considering non-idealities

  July 10, 2024    Tahmid

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Current-sensing is commonly used in power electronics and embedded systems, both for system monitoring, as well as to take decisions. Examples of common use cases for the latter are:

1. Monitoring inductor current for current-mode control in power converters
2. Monitoring converter current for overcurrent protection
3. Reading battery charge current to inform the charging process
4. Reading output current to compute output power to inform how to proceed in an MPPT charge controller

Use cases 1 and 2 require high-speed current measurements since they need to operate at either the converter's control frequency or based on a desired response time. Use cases 3 and 4, however, only require measuring "DC" current and so don't require high-speed current sense. The high-speed aspect ties to notions of slew rate and bandwidth for the amplifier. Other non-idealities, which I will describe here, affect even the DC behavior of the amplifier.

High-Side vs Low-Side Current Sensing

This article gives a good overview of the differences between high-side and low-side current sensing. Shown below are what they look like.

(a): High-side current sense
(b): Low-side current sense

Sense Resistor Selection

In both cases, the sense element is the series resistor Rs. By monitoring the voltage drop across Rs, you can compute the corresponding current from Ohm's Law: V=IR.

Tradeoffs for resistor selection include considerations for power and minimum sense voltage.

• Power dissipation in the resistor is given by I_rms²R_s. A larger resistor will correspond to larger power dissipation for the same current.
• Using a small resistor corresponds to a smaller sense voltage. When using a small sense resistor, you will use a current sense amplifier (CSA) to amplify the small sensed voltage to feed the corresponding circuit, which is often an ADC. A smaller resistor will correspond to requiring a larger gain in the amplifier or a greater ADC resolution.

High-side vs low-side

High-side current sense refers to placing the sense resistor in the "power" side without disrupting the power return or ground, enabling  the use of a common ground overall circuit scheme. Low-side current sense refers to placing the sense resistor in the "ground" side, thereby disrupting the power return/ground. If common-ground is not desired for your application, you can use the low-side sense scheme. 

In this article, we're looking at applications where you prefer high-side current sense!

Non-idealities Considerations and Circuit Design

In this application, I'm focusing on using a standard ultra-cheap op-amp instead of a dedicated current sense amplifier (such as INA180).

The op-amp I'm picking for this is the TL082 which I have on hand. The amplifier design is based on a standard differential amplifier configuration as shown in this article. The datasheet for the TL082 can be found on the TI website [1] [2]. LCSC shows the ultra-low cost of < $0.20 at volume!

The schematic for the current-sense amplifier (CSA) is shown below.

CSA implementation circuit (click to enlarge schematic)
R1=R2=2.2kΩ, R3=R4=5.6kΩ, Rs=0.5Ω, C1=C2=4.7uF, C3=0.1uF
VSNS+ = 12V

There are 3 parts to the output to consider:

1. VREF biases the output to 5V. Errors in the 5V reference will propagate to the output.
2. The diffamp gain is given by R3/R1 assuming R1=R2 and R3=R4. The input to the diffamp is given by the voltage across the sense resistor, which is the product of the current through it and its resistance.
3. The slope of the output voltage against current is negative due to the diffamp having negative gain. This is by design. See below.

We need to consider the amplifier non-idealities when designing the part. The ones we are considering, along with their impacts is shown below.

1. Input offset voltage
• This is a mismatch in the input voltage of the op-amp, due to the input-side design of the op-amp itself. This gets amplified and shows up as an error on the output. The TL082 is specced at 5mV typically. With our amplifier's gain of 5.6/2.2=2.54, this means that this offset shows up at the output as ~12.7mV. Given that our system's current gain magnitude is 1.27V/A, this corresponds to a 10mA error in current reading.
• Note that the offset can be positive or negative.
• Additionally, the offset varies over part tolerances and temperature, going up to as much as 20mV, which will correspond to closer to 40mA of error.
• Whether this is a problem or not depends on your application and desired current sense accuracy. You can perform an offset calibration to try to get rid of the steady-state error and only have to worry about the smaller temperature-dependent offset error. Alternately, you can use an opamp such as the TL081 which has additional pins to allow for offset nulling.
• Better opamps with lower offset can be used if the offset is an issue and cannot be solved by calibration.
2. Input bias and offset current
• A large input bias current will correspond to voltages dropped across R1 and R2, which will correspond to errors in the sensed voltage. The TL082 has bias currents in the 50pA-8nA range. Since this shows up on both inputs on this amplifier, the impact will depend on the mismatch between the input resistors. This will not be an issue in this particular application. In a low-side current-sense amplifier, the bias will show up differentially since one side will likely be grounded, so you will need to be more careful there.
• A large input offset current will correspond to mismatch in this voltage dropped across the input resistors, which will get amplified and show up as an error on the output. The TL082 has an input offset current spec between 25pA-4nA. The impact of this is the same as for the input offset voltage. Given that the input offset voltage spec is worse than this corresponding offset, this can be ignored for this application.
• The design will tend to get more sensitive to bias/offset current if you use larger input resistors, so you should be careful about that.
3. Input common-mode voltage range
• Rail-to-rail opamps allow the input voltages to go as high as the supply voltage and as low as the supply return. However, the TL082 is not a rail-to-rail opamp, so you need to be careful about making sure that the input voltage is within the desired spec. The datasheet outlines that the input voltage can go as high as the supply rail but can only go as low as 4V above supply return. That means that in our single-rail application, the input voltage cannot go below 4V.
• Note that this limit also means that you should not use the TL082 to buffer voltages below 4V!
• With the 5.6k and 2.2k resistors, as well as the 5V VREF, this is not a concern in our application! However, this is something to keep in mind!
4. Output voltage range
• You can notice that I flipped the + and - inputs on the op-amp relative to a non-inverting configuration. This gives negative gain, but why did I do this? By using VREF=5V, this then means that as current goes up, the output voltage will go down but will nominally be 5V. If I used VREF=0V and used a non-inverting configuration, that would result in the desired 0A output to be 0V. However, the TL082 cannot drive its output to within 200mV of the supply rail or return (or even worse if you have too low an output resistance!).
• This means that if the output sits at 200mV with no input, we cannot resolve currents below 158mA. However, if we sit at 5V, we don't have this issue since 5V is far out from either supply rail or GND!
• With a large enough current, the output still can't swing low enough, so the max current we can resolve is about (5V-0.2V)/1.27[V/A]=3.8A. Note that this would result in a large power in the sense resistor, so this is another constraint to consider!

Some additional considerations:

• VSNS+ is bounded between 4V and 14.75V. The lower bound maintains the op-amp's input common mode voltage range. The upper bound is given by the op-amp's supply voltage (=12V here). VSNS+ can go higher than 12V as long as the input to the op-amp pins is maintained to be at most 12V. The op-amp voltage at its non-inverting input is given by the equation below. With the circuit components implemented, this sets the upper bound of VSNS+ to 14.75V.
  
  
  
  
• Errors in the reference voltage VREF (=5V here) will propagate to the output. These can be accounted for with an initial calibration step. For best performance, use a voltage ref chip such as the LM4040. This will give better accuracy for the voltage reference.
• You can set the VREF to a higher voltage and increase the gain.
• You can use a voltage divider at the output to rescale the output to a lower range.
• You should add a low-pass anti-aliasing filter between the current-sense amplifier's output and the next-stage ADC.

Measurements

With steady state currents, the following output voltages were measured.

• 0.33A : 4.70V measured vs 4.58V expected : +2.6% error
• 0.94A : 3.73V measured vs 3.81V expected : -2.0% error

The input offset contributes output error - with no input, you can measure the output and find the offset. The component tolerances also contribute additional error.

For the purposes of this demonstrative application, this is deemed sufficient! In a wide range of applications, this could also be sufficient, especially in cases where the application is very cost-sensitive! I wanted to share some of the non-ideality considerations through this application and would love to hear if this has helped you understand them!

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Sine Wave Generation and Implementation using dsPIC33FJ

Sine Wave Generation and Implementation using dsPIC33FJ

  July 18, 2013    Tahmid

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Using the SG3525 PWM Controller - Explanation and Example: Circuit Diagram / Schematic of Push-Pull Converter

Using the SG3525 PWM Controller - Explanation and Example: Circuit Diagram / Schematic of Push-Pull Converter

  January 07, 2013    Tahmid

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PWM is used in all sorts of power control and converter circuits. Some common examples include motor control, DC-DC converters, DC-AC inverters and lamp dimmers. There are numerous PWM controllers available that make the use and application of PWM quite easy. One of the most popular of such controllers is the versatile and ubiquitous SG3525 produced by multiple manufacturers – ST Microelectronics, Fairchild Semiconductors, On Semiconductors, to name a few.

SG3525 is used extensively in DC-DC converters, DC-AC inverters, home UPS systems, solar inverters, power supplies, battery chargers and numerous other applications. With proper understanding, you can soon start using SG3525 yourself in such applications or any other application really that demands PWM control.

Before going on to the description and application, let’s first take a look at the block diagram and the pin layout.

Pins 1 (Inverting Input) and 2 (Non Inverting Input) are the inputs to the on-board error amplifier. If you are wondering what that is, you can think of it as a comparator that controls the increase or decrease of the duty cycle for the “feedback” that you associate with Pulse Width Modulation (PWM).

This functions either to increase or decrease the duty cycle depending on the voltage levels on the Inverting and Non-Inverting Inputs – pins 1 and 2 respectively.

• When voltage on the Inverting Input (pin 1) is greater than voltage on the Non-Inverting Input (pin 2), duty cycle is decreased.
• When voltage on the Non-Inverting Input (pin 2) is greater than voltage on the Inverting Input (pin 1), duty cycle is increased.

 

The frequency of PWM is dependent on the timing capacitance and the timing resistance. The timing capacitor (CT) is connected between pin 5 and ground. The timing resistor (RT) is connected between pin 6 and ground. The resistance between pins 5 and 7 (RD) determines the deadtime (and also slightly affects the frequency). 

The frequency is related to RT, CT and RD by the relationship:

With RT and RD in Ω and CT in F, f is in Hz.

Typical values of RD are in the range 10Ω to 47Ω. The range of values usable (as specified by the manufacturers of SG3525) is 0Ω to 500Ω.

RT must be within the range 2kΩ to 150kΩ. CT must be within the range 1nF (code 102) to 0.2µF (code 224). The oscillator frequency must be within the range 100Hz to 400kHz. There is a flip-flop before the driver stage, due to which your output signals will have frequencies half that of the oscillator frequency that is calculated using the above mentioned formula. So, if you are looking to use this for a 50Hz inverter, you require drive signals of 50Hz. So, the oscillator frequency must be 100Hz.

A capacitance connected between pin 8 and ground provides the soft-start functionality. The larger the capacitance, the larger the soft-start time. This means that the time taken to go from 0% duty cycle to the desired duty cycle or maximum duty cycle is larger. So, the duty cycle increases more slowly initially. Keep in mind that this only affects initial rate of increase of duty cycle, ie, the rate of increase of duty cycle after the SG3525 starts up.

Typical values of the soft-start capacitance lie within the range 1µF to 22µF depending on the desired soft-start time.

Pin 16 is the output from the voltage reference section. SG3525 contains an internal voltage reference module rated at +5.1V that is trimmed to provide a ±1% accuracy. This reference is often used to provide a reference voltage to the error amplifier for setting the feedback reference voltage. It can be directly connected to one of the inputs or a voltage divider can be used to further scale down the voltage.

Pin 15 is VCC – the supply voltage to the SG3525 that makes it run. VCC must lie within the range 8V to 35V. SG3525 has an under-voltage lockout circuit that prevents operation when VCC is below 8V, thus preventing erroneous operation or malfunction.

Pin 13 is VC – the supply voltage to the SG3525 driver stage. It is connected to the collectors of the NPN transistors in the output totem-pole stage. Hence the name VC. VC must lie within the range 4.5V to 35V. The output drive voltage will be one transistor voltage drop below VC. So when driving Power MOSFETs, VC should be within the range 9V to 18V (as most Power MOSFETs require minimum 8V to be fully on and have a maximum VGS breakdown voltage of 20V). For driving logic level MOSFETs, lower VC may be used. Care must be taken to ensure that the maximum VGS breakdown voltage of the MOSFET is not crossed. Similarly when the SG3525 outputs are fed to another driver or IGBT, VC must be selected accordingly, keeping in mind the required voltage for the device being fed or driven. It is common practice to tie VC to VCC when VCC is below 20V.

Pin 12 is the Ground connection and should be connected to the circuit ground. It must share a common ground with the device it drives.

Pins 11 and 14 are the outputs from which the drive signals are to be taken. They are the outputs of the SG3525 internal driver stage and can be used to directly drive MOSFETs and IGBTs. They have a continuous current rating of 100mA and a peak rating of 500mA. When greater current or better drive is required, a further driver stage using discrete transistors or a dedicated driver stage should be used. Similarly a driver stage should be used when driving the device causing excessive power dissipation and heating of SG3525. When driving MOSFETs in a bridge configuration, high-low side drivers or gate-drive transformers must be used as the SG3525 is designed only for low-side drive.

Pin 10 is shutdown. When this pin is low, PWM is enabled. When this pin is high, the PWM latch is immediately set. This provides the fastest turn-off signal to the outputs. At the same time the soft-start capacitor is discharged with a 150µA current source. An alternative method of shutting down the SG3525 is to pull either pin 8 or pin 9 low. However, this is not as quick as using the shutdown pin. So, when quick shutdown is required, a high signal must be applied to pin 10. This pin should not be left floating as it could pick up noise and cause problems. So, this pin is usually held low with a pull-down resistor.

Pin 9 is compensation. It may be used in conjunction with pin 1 to provide feedback compensation.

Now that we’ve seen the function of each pin, let’s design a circuit with the SG3525 and see how it is put to use practically.

Let’s make a circuit running at 50kHz, driving MOSFETs (in a push-pull configuration) that drive a ferrite core which then steps up the high frequency AC and then is rectified and filtered to give a 290V regulated output DC that can be used to run one or more CFLs.

For the turns calculation, check out my article "Ferrite Transformer Turns Calculation for High-Frequency/SMPS Inverter": http://tahmidmc.blogspot.com/2012/12/ferrite-transformer-turns-calculation.html

So here’s the circuit (click on the circuit to enlarge the image):

Let’s analyze it and see what I’ve done.

You can firstly see that the supply voltage has been provided and ground has been connected. Also notice that VC has been connected to VCC. I’ve added a bulk and a decoupling capacitor across the supply pins. The decoupling capacitor (0.1µF) should be placed as close to the SG3525 as possible. You should always use this in all your designs. Do not omit the bulk capacitor either, although you may use a smaller value.

Let’s see pins 5, 6 and 7. I’ve added a small resistance RD (between pins 5 and 7) that provides a little deadtime. I’ve connected RT between pin 6 and ground and CT between pin 5 and ground. RD = 22Ω, CT = 1nF (Code: 102) and RT = 15kΩ. This gives an oscillator frequency of:

As the oscillator frequency is 94.6kHz, the switching frequency is 0.5 * 94.6kHz = 47.3kHz and this is close enough to our target frequency of 50kHz. Now if you had needed 50kHz accurate, then the best way would have been to use a pot (variable resistor) in series with RT and adjust the pot, or to use a pot (variable resistor) as RT, although I prefer the first as it allows for fine tuning the frequency.

Let’s look at pin 8 now. I’ve connected a 1µF capacitor from pin 8 to ground and this provides a small soft-start. I’ve avoided using too large a soft-start as the slow duty cycle increase (and thus the slow increase in voltage) causes problems when using CFLs at the output.

Let’s look at pin 10 now. Initially it’s pulled up to VREF with a pull-up resistor. So, PWM is disabled and does not run. However, when the switch is on, pin 10 is now at ground and so PWM is enabled. So, we’ve made use of the SG3525 shutdown option (via pin 10). Thus the switch acts like an on/off switch.

Pin 2 is connected to VREF and is thus at a potential of +5.1V (±1%). The output of the converter is connected to pin 1 through a voltage divider with resistances 56kΩ and 1kΩ. Voltage ratio is 57:1. At feedback “equilibrium”, voltage at pin 1 is 5.1V as well as this is the target of the error amplifier – to adjust the duty cycle to adjust the voltage at pin 1 so that it is equal to that of pin 2. So, when voltage at pin 1 is 5.1V, voltage at output is 5.1V * 57 = 290.7V and this is close enough to our 290V target. If greater accuracy is required, one of the resistors can be either replaced with a pot or in series with a pot and the pot adjusted to give required reading.

The parallel combination of the resistor and capacitor between pins 1 and 9 provides feedback compensation. I won’t go into detail into feedback compensation as it is a vast topic on its own.

Pins 11 and 14 drive the MOSFETs. There are resistors in series with the gate to limit gate current. The resistors from gate-to-source ensure that MOSFETs don’t get accidentally turned on.

So that’s about it. You can see that this is quite an easy circuit to design. If you’ve understood all of this, you can now design circuits with SG3525 yourself. Try to make a few, eg for 50Hz output and with isolated feedback. If you can’t don’t worry, I’ll put up another article with a few more circuits using SG3525 so that you become completely clear with it (if you haven’t already).

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Reference documents:

SG3525 datasheet: www.onsemi.com/pub/Collateral/SG3525A-D.PDF

Ferrite Transformer Turns Calculation for High-Frequency/SMPS Inverter: http://tahmidmc.blogspot.com/2012/12/ferrite-transformer-turns-calculation.html

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Ferrite Transformer Turns Calculation for High-Frequency/SMPS Inverter

Ferrite Transformer Turns Calculation for High-Frequency/SMPS Inverter

  December 23, 2012    Tahmid

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On different forums, I often find people asking for help in calculating the required turns for a ferrite transformer they are going to use in high-frequency/SMPS inverters. In a high-frequency/SMPS inverter, the ferrite transformer is used in the step-up/boost stage where the low voltage DC from the battery is stepped up to high voltage DC. In this situation, there are really only two choices when selecting topology – push-pull and full-bridge. For transformer design, the difference between a push-pull and a full-bridge transformer for same voltage and power will be that the push-pull transformer will require a center tap, meaning it will require twice the number of primary turns as the full-bridge transformer.

Calculation of required turns is actually quite simple and I’ll explain this here.

For explanation, I’ll use an example and go through the calculation process.

Let’s say the ferrite transformer will be used in a 250W inverter. The selected topology is push-pull. The power source is a 12V battery. Output voltage of the DC-DC converter stage will be 310V. Switching frequency is 50kHz. The selected core is ETD39. Remember that the output of the transformer will be high frequency AC (50kHz square wave in this case). When I refer to an output of high voltage DC (eg 310VDC mentioned above), this is the DC output obtained after rectification (using ultrafast recovery diodes configured as bridge rectifier) and filtration (using LC filter).

During operation, the battery voltage does not stay fixed at 12V. With high loads, the voltage will be less than 12V. With low loads and near-fully charged battery, the voltage may be higher than 13V. So, it must be kept in mind that the input voltage is not constant, but is variable. In inverters, the battery low-cut is usually set at 10.5V. So, we’ll take this as our lowest possible input voltage.

Vinmin = 10.5V

The formula for calculating the number of required primary turns is:

 

For our push-pull transformer, this will be one-half the required number of turns.

N_pri means number of primary turns; N_sec means number of secondary turns; N_aux means number of auxiliary turns and so on. But just N (with no subscript) refers to turns ratio.

For calculating the required number of primary turns using the formula, the parameters or variables that need to be considered are:

• Vin_(nom) – Nominal Input Voltage. We’ll take this as 12V. So, Vin_(nom) = 12.
• f – The operating switching frequency in Hertz. Since our switching frequency is 50kHz, f = 50000.
• B_max – Maximum flux density in Gauss. If you’re used to using Tesla or milliTesla (T or mT) for flux density, just remember that 1T = 10⁴ Gauss. B_max really depends on the design and the transformer cores being used. In my designs, I usually take B_max to be in the range 1300G to 2000G. This will be acceptable for most transformer cores. In this example, let’s start with 1500G. So B_max = 1500. Remember that too high a B_max will cause the transformer to saturate. Too low a B_max will be under utilizing the core.
• A_c – Effective Cross-Sectional Area in cm². You will get this information from the datasheets of the ferrite cores. A_c is also sometimes referred to as A_e. For ETD39, the effective cross-sectional area given in the datasheet/specification sheet (I’m referring to TDK E141. You can download it from here: www.tdk.co.jp/tefe02/e141.pdf  ), the effective cross-sectional area (in the specification sheet, it’s referred to as A_e but as I’ve said, it’s the same thing as A_c) is given as 125mm². That is equal to 1.25cm². So, A_c = 1.25 for ETD39.

 

So now, we’ve obtained the values of all required parameters for calculation Npri – the number of required primary turns.

Vin_(nom) = 12                                        f = 50000                              B_max = 1500                          A_c = 1.25

Plugging these values into the formula:

                        N_pri = 3.2

We won’t be using fractional windings, so we’ll round off N_pri to the nearest whole number, in this case, rounded down to 3 turns. Now, before we finalize this and select N_pri = 3, we better make sure that B_max is still within acceptable bounds. As we’ve decreased the number of turns from the calculated figure (down to 3.0 from 3.2), B_max will increase. We now need to figure out just how much B_max has increased and if that is still an acceptable value.

Vin_(nom) = 12                 f = 50000                     N_pri = 3                         A_c = 1.25

 

                                                                   B_max = 1600

The new value of B_max is well within acceptable bounds and so we can proceed with N_pri = 3.

So, we now know that for the primary, our transformer will require 3 turns + 3 turns.

In any design, if you need to adjust the values, you can easily do so. But always remember to check that B_max is acceptable.

• For example, if for construction difficulties, winding 3 turns + 3 turns becomes difficult, you may use 2 turns + 2 turns or 4 turns + 4 turns. Increasing number of turns won’t hurt – you’ll just be under utilizing the core. However, decreasing number of turns increases B_max, so just recheck to make sure B_max is okay. The range I’ve stated for B_max (1300G to 2000G) is just an estimate. It will work for most cores. However, with many cores, you can go higher to decrease the number of turns. Going lower will just be under utilizing the core, but may sometimes be required if number of turns is too low. 

 

• I’ve started off with a set B_max and gone on to calculate N_pri from there. You can also assign a value of N_pri and then check if B_max is okay. If not, you can then increase or decrease N_pri as required and then check if B_max is okay, and repeat this process until you get a satisfactory result. For example, you may have set Npri = 2 and calculated Bmax and decided that this was too high. So, you set Npri = 3 and calculated Bmax and decided it was okay. Or you may have started with Npri = 4 and calculated Bmax and decided that it was too low. So, you set Npri = 3 and calculated Bmax and decided it was okay.

Now it’s time to move on to the secondary. The output of our DC-DC converter is 310V. So, the transformer output must be 310V at all input voltages, from all the way up from 13.5V to all the way down to 10.5V. Naturally, feedback will be implemented to keep the output voltage fixed even with line and load variations – changes due to battery voltage change and also due to load change. So, some headroom must be left for feedback to work. So, we’ll design the transformer with secondary rated at 330V. Feedback will just adjust the voltage required by changing the duty cycle of the PWM control signals. Besides feedback, the headroom also compensates for some of the losses in the converter and thus compensates for the voltage drops at different stages – for example, in the MOSFETs, in the transformer itself, in the output rectifiers, output inductor, etc.

This means that the output must be capable of supplying 330V with input voltage equal to 10.5V and also input voltage equal to 13.5V. For the PWM controller, we’ll take maximum duty cycle to be 98%. The gap allows for dead-time.

At minimum input voltage (when Vin = Vinmin), duty cycle will be maximum. Thus duty cycle will be 98% when Vin = 10.5 = Vinmin. At maximum duty cycle = 98%, voltage to transformer = 0.98 * 10.5V = 10.29V.

So, voltage ratio (secondary : primary) = 330V : 10.29V = 32.1

Since voltage ratio (secondary : primary) = 32.1, turns ratio (secondary : primary) must also be 32.1 as turns ratio (secondary : primary) = voltage ratio (secondary : primary). Turns ratio is designated by N. So, in our case, N = 32.1 (I’ve taken N as the ratio secondary : primary).

N_pri = 3

N_sec = N * N_pri = 32.1 * 3 = 96.3

Round off to the nearest whole number. N_sec = 96.

Thus 96 turns are required for the secondary. With proper implementation of feedback, a constant 310VDC output will be obtained throughout the entire input voltage range of 10.5V to 13.5V.

Here, one thing to note is that even though I took 98% as the maximum duty cycle, maximum duty cycle in practice will be smaller since our transformer was calculated to provide 330V output. In the circuit, the output will be 310V, so the duty cycle will be even lower. However, the advantage here is that you can be certain that the output will not drop below 330V even with heavy loads since a large enough headroom is provided for feedback to kick in and maintain the output voltage even at high loads.

If any auxiliary windings are required, the required turns can be easily calculated. Let me show with an example. Let’s say we need an auxiliary winding to provide 19V. I know that the output 310V will be regulated, whatever the input voltage may be, within the range initially specified (Vinmin to Vinmax – 10.5V to 13.5V). So, the turns ratio for the auxiliary winding can be calculated with respect to the secondary winding. Let’s call this turns ratio (secondary : auxiliary) N_A.

N_A = N_sec / N_aux = V_sec / (V_aux + V_d). V_d is the output diode forward drop. Let’s assume that in our application, a schottky rectifier with a V_d = 0.5V is used.

So, N_A = 310V / 19.5V =15.9

N_sec / N_aux = N_A

N_aux = N_sec / N_A = 96 / 15.9 = 5.96

Let’s round off N_aux to 6 and see what the output voltage is.

V_sec / (V_aux + V_d) = N_A = N_sec / N_aux = 96 / 6 =16.0

(V_aux + V_d) = V_sec / N_A = 310V / 16.0 = 19.375V

V_aux = 19.375V – 0.5V = 18.875V (rounded off)

I would say that’s great for an auxiliary supply. If in your calculations you come to a voltage that is too far off the required target voltage and thus greater accuracy is required, take V_aux as something higher and use a voltage regulator.

For example, if in our previous example, instead of18.875V we had gotten 19.8V but needed more accuracy, we could've used 24V or thereabouts and used a voltage regulator to give 19V output.

So, there we have it. Our transformer has 3 turns + 3 turns for primary, 96 turns for secondary and 6 turns for auxiliary.

Here’s our transformer:

Calculating required number of turns for a transformer is actually a simple task and I hope that I could help you understand how to do this. I hope this tutorial helps you in your ferrite transformer designs. Do let me know your comments and feedback.

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