Embedded Systems and Power Electronics

Total Pageviews

About Me

My photo
I am currently a PhD student at UC Berkeley, following a 6-year journey working at Apple after my undergrad years at Cornell University. I grew up in Dhaka, Bangladesh where my interest in electronics was cultivated, resulting in the creation of this blog.

BTemplates.com

Powered by Blogger.

Jan 1, 2025

Sprucing up an old scope: fixing the dials on the Owon SDS6062V


I got the Owon SDS6062V scope back in 2014 when it seemed a great deal compared to brands like Tektronix and much better than cheaper analog or portable digital scopes. These days, I've been using the Rigol DS1202 for hobby projects which is a better part, in my opinion. Of course, none of these are as nice as the Keysight MSOX scopes at work.

I've demonstrated the Owon scope in previous projects such as Generating complementary PWM with adjustable deadtime for the RP2040 and Stereo audio player using the PIC32, MCP4822, microSD card and the MDDFS library (back in 2015!). The dials on the front panel seem to all be "broken". When turning the dials, the response is erratic. For example, when turning the time division dial clockwise, sometimes the time division goes up, sometimes down, sometimes it jumps all the way down to the minimum or will jump up and back down. The same is true for all the other dials. Searching online revealed that this seems to be a common issue with the scope, with the encoders having worn out with age. Some sources suggested using filter caps on the output of the encoders (dials). However, this didn't help with mine. So I decided to just replace the encoders themselves.

The instructions for taking the scope apart and getting to the front panel PCB that houses the encoders is very well documented in the service manual. I uploaded a copy of the Owon service manual on Drive: Owon Service Manual (Drive mirror)

 

Fig. 1 - Owon SDS-6062V oscilloscope with original dials and caps

Fig. 2 - Scope with the encoders replaced

Fig. 3 - The front panel PCB with the encoders soldered

After accessing the front panel PCB, I desoldered all the encoders. I could not find part numbers for these encoders and just went ahead and bought a standard 10-pack of encoders (Amazon link). Fig. 4 shows that the ordered parts are quite a bit taller than the ones on the scope. However, with the different encoder caps as shown in Fig. 5, the height difference is substantially removed. When I was looking online for which encoders to order, I found several sources suggesting ordering "standard encoders" without part numbers. So my hope here is that if someone is trying to change the encoders on their scope, they have a reference part to order if they're lost.
Fig. 4 - Encoders for the scope. Left = encoders removed from the scope PCB. Right = encoders ordered from Amazon.

Fig. 5 - Encoders with their corresponding caps mounted. Left = encoders removed from the scope PCB. Right = encoders ordered from Amazon.

Once the new encoders are soldered into the panel, the scope dials now worked as expected. The replacement encoders I used all have steps in them. The scope's horizontal position encoders did not have steps. I didn't mind this at all and actually quite like the additional tactile feedback.

I am also a big fan of the look of the new encoder caps! The spruced up scope is shown in Fig. 2. This was a simple fix, but I wanted to document the service manual and the encoders here for someone else to find useful! This breathes new life into this trusty scope and hopefully it can continue functioning!

Here are some fun shots of the interior of the scope!


Dec 31, 2024

Insights from repairing a 30V 5A power supply (BPS-305)


When I started working on a project (hopefully more on that soon), I reached out for an old 30V 5A power supply (Lavolta BPS-305). I rotated the voltage dial to try to get to 24V and observed that the voltage would not go past 15V, even though it is rated for 30V. Even though this supply was a few years old, I had not personally used it before. So, it wasn't clear whether it was a previously-functioning supply that stopped working, or whether it was always broken.

Fig. 1 - Lavolta BPS-305 power supply

Upon some more poking and prodding, I identified that the power supply had several issues:

  1. Output voltage only goes up to about 15V instead of 30V max.
  2. Output voltage is not stable and fluctuates at steady state, appearing unregulated. See video below.
  3. Output voltage flickers when relays switch around ~7V and ~14V and the relays keep flickering unless the voltage is moved far away from the transition points.
  4. Output current measurement (when HI/LO button is pressed down to LO) is off by a factor of 2.
  5. Output current measurement (when HI/LO button is pressed up to HI) displays zero.
Output voltage unstable at "steady state" - moving between 10.2V to 11.1V with a fixed output load

Hopeful that I can repair the supply, I opened it up. Noticing a relatively simple one-layer PCB, I set out to find a schematic or other reference for the supply. This is where I realized that many many (low-cost) 30V 5A power supplies are based on the same couple designs. I'll link to a few useful resources here that I came across during my search:

Instead of going through all my investigations, I'll highlight a few standouts here.

Broken potentiometers

After lots of investigating, the key offenders were 2 broken potentiometers. Referring to the file PS305D Schematic Main in the Drive link, these are VR104 and VR102. These are shown below in Fig. 2.
Fig. 2 - The culprits. VR104 is marked 502 (5kΩ) and VR102 is marked 501 (500Ω). Both parts measure open at component ends.

VR104 is used for output voltage feedback. Once this part was replaced with a functioning 5kΩ pot, the output voltage was now stable and would go all the way up to 30V. The pot is trimmed until the max output voltage is 30V.

VR102 sets the max output current when the HI/LO button is released (HI -> 5A current limit). There was no current limit being set in this setting with the faulty part. Since I did not have a 500Ω pot on hand, I replaced VR102 with a 5kΩ pot in parallel with a 470Ω resistor. This allows tuning the resistance as shown in Fig. 3. Fig. 4 shows the parallel 470Ω resistor soldered on the back side of the board. Once these parts were provisioned, the 5kΩ pot was trimmed until the max output current was set to 5A. The red dot in Fig. 3 indicates the final trimmed resistance.

Fig. 3 - combined resistance of 5kΩ pot in parallel with 470Ω resistance as the pot is trimmed.

Fig. 4 - soldered 470Ω resistor in parallel with VR102

FIg. 5 - the two blue potentiometers replace the broken ones in Fig. 2

Tuning the current display

Fig. 6 - Output current reading 6.89A when the real measured value is 5A
Fig. 7 - DMM on the PSU; the trim pots are the blue components near each chip. Left display is for current and the corresponding trimpot is VR211. Right display is for voltage and the corresponding trimpot is VR201.

When the HI/LO button is pushed down to the LO position, the PSU's output current limit is set to 2.5A tuned by VR101. When the HI/LO button is at the HI position, the output limit is set by VR102 (and the parallel 470Ω resistor) as described previously. However, there was a fair bit of error on this reading, as shown in Fig. 6. By adjusting VR305 (see PS305D Schematic Controls in the Drive link) in conjunction with the reference voltage set by the blue trimpot VR211 (see PS305D Schematic Display in the Drive link) in Fig. 7, the output current can be tuned. Since VR211 affects the reference voltage for the current meter, adjusting it affects both the HI and LO current readings. The procedure then was to set the switch to HI and then tune VR211; once that is corrected, switch to LO and then tune VR305.

Relay-selectable transformer secondary winding

Fig. 8 - secondary selection scheme with relay

Because the regulation stage in the power supply is based on a linear regulator, the difference between the input and output power is dissipated as heat. Since the power supply has a large selectable output range, this would result in very high power dissipation in the regulator at lower input voltages. To overcome this drawback and reduce the power dissipation, the power supply utilizes a selector circuit on the secondary as shown in Fig. 8.

As an example, let's consider that the output power is desired to be 3.3V. Suppose the input voltage post-rectifier is 40V (which is the case between S3-S0 for the BPS-305). At an output current of 3A, the power dissipated in the regulator would be roughly: Pout-Pin = Vout*Iout - Vin*Iin ~ (Vout-Vin)*Iout = 110.1W.  All this for only 13.2W of output power. At lower output voltages and higher output currents, this gets even worse!

By using the scheme shown in Fig. 8, the voltage at the input of the regulator is selected based on the desired output voltage to reduce power dissipation. With the example above, now suppose that for 3.3V, the input to the regulator is 14.8V, the power dissipation is reduced to 34.5W now! That's 75W less than the previous example!

For my unit, the voltage bins transitions happen for output voltages 8V, 15V, 21V and 30V. This is a good design decision rather than having a fixed 40V input for the regulator.

Output testing

For testing the output, different resistor combinations were used as the load. In addition, a constant current circuit was used even as the output voltage is varied. A simple circuit can be designed using the jellybean LM317 part. The datasheet shows an example circuit in Section 9.3.3 (Precision Current-Limiter Circuit).
Fig. 9 - constant current circuit using LM317

The output (ADJUST pin) is tied to GND for testing. Using R1 = 4.7Ω provides a ~250mA constant current load. Similarly, R1 is swapped out for lower values for higher currents. It is important to have a heatsink mounted on the LM317, especially at higher voltages. This constant current value was also used to validate the output current display across PSU output voltages.

Other observations

  1. The logic GND for the electronics are shorted to the positive output instead of the negative output. Even though the circuits in the PSU closely reflect those of PS305D Schematic Main/Display/Controls, this grounding scheme is reflected in hy_3005_dc_power_supply.
  2. Many of these 30V 5A power supplies seem to be based on a couple base designs with slight tweaks in implementation.
  3. The build quality appears shoddy. Many components were haphazardly soldered - many caps weren't fully seated. The fan wires run adjacent to (and touch) the (potentially very hot) heatsink for the transistors. However, none of these appear to impact functionality, at least in the short term.

Jul 10, 2024

A low-cost high-side current sense amplifier: design considering non-idealities


Current-sensing is commonly used in power electronics and embedded systems, both for system monitoring, as well as to take decisions. Examples of common use cases for the latter are:
  1. Monitoring inductor current for current-mode control in power converters
  2. Monitoring converter current for overcurrent protection
  3. Reading battery charge current to inform the charging process
  4. Reading output current to compute output power to inform how to proceed in an MPPT charge controller
Use cases 1 and 2 require high-speed current measurements since they need to operate at either the converter's control frequency or based on a desired response time. Use cases 3 and 4, however, only require measuring "DC" current and so don't require high-speed current sense. The high-speed aspect ties to notions of slew rate and bandwidth for the amplifier. Other non-idealities, which I will describe here, affect even the DC behavior of the amplifier.

High-Side vs Low-Side Current Sensing

This article gives a good overview of the differences between high-side and low-side current sensing. Shown below are what they look like.

(a): High-side current sense
(b): Low-side current sense

Sense Resistor Selection

In both cases, the sense element is the series resistor Rs. By monitoring the voltage drop across Rs, you can compute the corresponding current from Ohm's Law: V=IR.

Tradeoffs for resistor selection include considerations for power and minimum sense voltage.
  • Power dissipation in the resistor is given by Irms2Rs. A larger resistor will correspond to larger power dissipation for the same current.
  • Using a small resistor corresponds to a smaller sense voltage. When using a small sense resistor, you will use a current sense amplifier (CSA) to amplify the small sensed voltage to feed the corresponding circuit, which is often an ADC. A smaller resistor will correspond to requiring a larger gain in the amplifier or a greater ADC resolution.

High-side vs low-side

High-side current sense refers to placing the sense resistor in the "power" side without disrupting the power return or ground, enabling  the use of a common ground overall circuit scheme. Low-side current sense refers to placing the sense resistor in the "ground" side, thereby disrupting the power return/ground. If common-ground is not desired for your application, you can use the low-side sense scheme. 

In this article, we're looking at applications where you prefer high-side current sense!

Non-idealities Considerations and Circuit Design

In this application, I'm focusing on using a standard ultra-cheap op-amp instead of a dedicated current sense amplifier (such as INA180).

The op-amp I'm picking for this is the TL082 which I have on hand. The amplifier design is based on a standard differential amplifier configuration as shown in this article. The datasheet for the TL082 can be found on the TI website [1] [2]. LCSC shows the ultra-low cost of < $0.20 at volume!

The schematic for the current-sense amplifier (CSA) is shown below.

CSA implementation circuit (click to enlarge schematic)
R1=R2=2.2kΩ, R3=R4=5.6kΩ, Rs=0.5Ω, C1=C2=4.7uF, C3=0.1uF
VSNS+ = 12V


There are 3 parts to the output to consider:
  1. VREF biases the output to 5V. Errors in the 5V reference will propagate to the output.
  2. The diffamp gain is given by R3/R1 assuming R1=R2 and R3=R4. The input to the diffamp is given by the voltage across the sense resistor, which is the product of the current through it and its resistance.
  3. The slope of the output voltage against current is negative due to the diffamp having negative gain. This is by design. See below.

We need to consider the amplifier non-idealities when designing the part. The ones we are considering, along with their impacts is shown below.

  1. Input offset voltage
    • This is a mismatch in the input voltage of the op-amp, due to the input-side design of the op-amp itself. This gets amplified and shows up as an error on the output. The TL082 is specced at 5mV typically. With our amplifier's gain of 5.6/2.2=2.54, this means that this offset shows up at the output as ~12.7mV. Given that our system's current gain magnitude is 1.27V/A, this corresponds to a 10mA error in current reading.
    • Note that the offset can be positive or negative.
    • Additionally, the offset varies over part tolerances and temperature, going up to as much as 20mV, which will correspond to closer to 40mA of error.
    • Whether this is a problem or not depends on your application and desired current sense accuracy. You can perform an offset calibration to try to get rid of the steady-state error and only have to worry about the smaller temperature-dependent offset error. Alternately, you can use an opamp such as the TL081 which has additional pins to allow for offset nulling.
    • Better opamps with lower offset can be used if the offset is an issue and cannot be solved by calibration.
  2. Input bias and offset current
    • A large input bias current will correspond to voltages dropped across R1 and R2, which will correspond to errors in the sensed voltage. The TL082 has bias currents in the 50pA-8nA range. Since this shows up on both inputs on this amplifier, the impact will depend on the mismatch between the input resistors. This will not be an issue in this particular application. In a low-side current-sense amplifier, the bias will show up differentially since one side will likely be grounded, so you will need to be more careful there.
    • A large input offset current will correspond to mismatch in this voltage dropped across the input resistors, which will get amplified and show up as an error on the output. The TL082 has an input offset current spec between 25pA-4nA. The impact of this is the same as for the input offset voltage. Given that the input offset voltage spec is worse than this corresponding offset, this can be ignored for this application.
    • The design will tend to get more sensitive to bias/offset current if you use larger input resistors, so you should be careful about that.
  3. Input common-mode voltage range
    • Rail-to-rail opamps allow the input voltages to go as high as the supply voltage and as low as the supply return. However, the TL082 is not a rail-to-rail opamp, so you need to be careful about making sure that the input voltage is within the desired spec. The datasheet outlines that the input voltage can go as high as the supply rail but can only go as low as 4V above supply return. That means that in our single-rail application, the input voltage cannot go below 4V.
    • Note that this limit also means that you should not use the TL082 to buffer voltages below 4V!
    • With the 5.6k and 2.2k resistors, as well as the 5V VREF, this is not a concern in our application! However, this is something to keep in mind!
  4. Output voltage range
    • You can notice that I flipped the + and - inputs on the op-amp relative to a non-inverting configuration. This gives negative gain, but why did I do this? By using VREF=5V, this then means that as current goes up, the output voltage will go down but will nominally be 5V. If I used VREF=0V and used a non-inverting configuration, that would result in the desired 0A output to be 0V. However, the TL082 cannot drive its output to within 200mV of the supply rail or return (or even worse if you have too low an output resistance!).
    • This means that if the output sits at 200mV with no input, we cannot resolve currents below 158mA. However, if we sit at 5V, we don't have this issue since 5V is far out from either supply rail or GND!
    • With a large enough current, the output still can't swing low enough, so the max current we can resolve is about (5V-0.2V)/1.27[V/A]=3.8A. Note that this would result in a large power in the sense resistor, so this is another constraint to consider!

Some additional considerations:
  • VSNS+ is bounded between 4V and 14.75V. The lower bound maintains the op-amp's input common mode voltage range. The upper bound is given by the op-amp's supply voltage (=12V here). VSNS+ can go higher than 12V as long as the input to the op-amp pins is maintained to be at most 12V. The op-amp voltage at its non-inverting input is given by the equation below. With the circuit components implemented, this sets the upper bound of VSNS+ to 14.75V.

  • Errors in the reference voltage VREF (=5V here) will propagate to the output. These can be accounted for with an initial calibration step. For best performance, use a voltage ref chip such as the LM4040. This will give better accuracy for the voltage reference.
  • You can set the VREF to a higher voltage and increase the gain.
  • You can use a voltage divider at the output to rescale the output to a lower range.
  • You should add a low-pass anti-aliasing filter between the current-sense amplifier's output and the next-stage ADC.

Measurements

With steady state currents, the following output voltages were measured.
  • 0.33A : 4.70V measured vs 4.58V expected : +2.6% error
  • 0.94A : 3.73V measured vs 3.81V expected : -2.0% error

The input offset contributes output error - with no input, you can measure the output and find the offset. The component tolerances also contribute additional error.

For the purposes of this demonstrative application, this is deemed sufficient! In a wide range of applications, this could also be sufficient, especially in cases where the application is very cost-sensitive! I wanted to share some of the non-ideality considerations through this application and would love to hear if this has helped you understand them!

Jul 3, 2024

Generating complementary PWM with adjustable deadtime for the RP2040


I have previously discussed the benefits of using the Raspberry Pi Pico, leveraging the easy-to-program Micropython along with the capable hardware peripherals: 2023 Updates: PhD; Pi Pico and Quick and dirty PIC16F72 programmer with the Pico

Several articles in the blog have previously described applications of PWM in embedded systems, such as Stereo audio player using the PIC32, MCP4822, microSD card and the MDDFS libraryDC motor control with PIC16F877A - Practical example of PIC PWM and Generation of sine wave using SPWM in PIC16F684.

Complementary PWM signals with 500ns deadtime

The underlying RP2040 in the Pi Pico provides an easy-to-use and still powerful and flexible set of PWM peripherals that can enable a wide range of applications. A common requirement in power electronics is the generation of complementary PWM signals. For example, the complementary PWM signals are used in a synchronous buck converter, shown below, to drive the switches S1 and S2.

Synchronous Buck Converter
Image source: https://commons.wikimedia.org/wiki/File:300px-Synch_buck.PNG

To prevent shoot-through, a deadtime is employed. Shoot-through is the event when both S1 and S2 are turned on, causing a large current through them due to shorting across the supply voltage. Even if the generated PWM signals are non-overlapping (ie S1 and S2 are never turned on together), delays in the circuitry - through the gate drivers and the power switches themselves - can still result in shoot-through conditions. In a severe case, the shoot-through can cause damage to the switches, blowing them out. In a more moderate case, small overlap times can result in reduced efficiency due to wasted power, but not necessarily damage to the switches. To combat this issue, a deadtime is inserted between the S1 and S2 driving signals. This is an amount of time when both switch control signals are zero allowing for system transients to settle out. How large it should be depends on the circuit parameters and behavior.

In many cases, gate drivers can have built-in features to insert dead-times, such as the LM5106. However, the ability to generate this in the microcontroller itself gives greater flexibility in the selection of gate driver. Further, it allows tuning the time easily in software rather than needing to change hardware components to change deadtimes.

Fortunately, the Pi Pico makes it fairly straightforward to do this!

The details of the PWM peripheral are outlined in the RP2040 datasheet section 4.5. You can find the code sample here: https://github.com/SyedTahmidMahbub/comppwm_rp2040

The corresponding source code is copied below for convenience:


The RP2040 has 8x PWM slices, each with 2 channels. The complementary PWM waveforms are produced on these 2 channels (A and B) on a given slice. The slice to GPIO mapping is shown below.
PWM slice+channel mapping to GPIO pins
Image source: RP2040 datasheet section 4.5.2

The key aspects of the code are:
  • Use Micropython to init PWM for the associated GPIO pins (A and B).
  • Alter RP2040 registers to configure for complementary PWM. This consists of two settings being changed.
    • Invert channel B relative to channel A.
    • Use center-aligned (phase-correct) PWM instead of edge-aligned. This ensures that the deadtime is applied to both rising and falling edges of channel A. If edge-aligned PWM was used, the channels would be set high together and the deadtime would only be applied on the falling edge of channel A.
  • The deadtime is applied to channel B such that channel A's duty cycle corresponds to the desired/set duty cycle.
  • The duty cycles corresponding to both channels A and B are updated with one register write.
  • The frequency of the output PWM using center-aligned/phase-correct mode is half that when using the default edge-aligned mode.
An example of phase-correct/center-aligned PWM operation is shown in the figure below, taken from the RP2040 datasheet.

Image source: RP2040 datasheet section 4.5.2.1

To generate the complementary signal on channel B, the duty cycle is computed as the sum of the pulse count corresponding to the desired duty cycle and the desired deadtime ticks. With a 125MHz clock for the RP2040 and default clock/divider settings, this corresponds to 8ns per tick. The inversion of channel B then ensures the production of the desired complementary setting.

Shown below are waveforms for GP16 (PWM 0A) and GP17 (PWM0B) for 100kHz PWM, 25% duty cycle and a 504ns deadtime. The deadtime can be verified by recognizing that it corresponds to one horizontal division, which is set to 500ns.

Complementary PWM signals with 500ns deadtime

Taking a zoomed out view of the waveform highlights the 100kHz frequency and illustrates the complementary PWM generation over multiple cycles, as shown below.

3 cycles of 100kHz PWM complementary signals

A natural use case for this generated complementary PWM signal is to control a synchronous buck converter to achieve high efficiency step down operation. Since Micropython will limit the design of a fast control loop, applications where the high frequency PWM is coupled with a low-bandwidth controller make for a natural home for this use case. A solar MPPT battery charger would make for an ideal usage scenario. Alternately, if the same configuration technique is applied in C, fast control loops can then be designed and implemented.

Mar 23, 2024

Electrolytic caps over frequency: why is my 470uF actually 20uF?


While using an LCR meter to measure a 470uF cap in lab, the meter read the expected values at low frequency (100 Hz). But when measured at 100 kHz, the meter read 19uF. While I expected a capacitance drop due to parasitic inductance, I was still surprised at this sharp of a drop. I decided to dig further.

Simplistically, we can model a real capacitor as the following circuit:

Simplistic capacitor model including parasitic elements

C is the main capacitor and the other terms represent parasitic elements: Rs and Ls are the series resistances and inductances, whereas Rp is the parallel (leakage) resistance.

When using ceramic capacitors, datasheets often provided impedance charts over frequency and clearly highlight the self-resonant frequency. Let's consider the C3216X5R1V226M160AC. The impedance chart for the part is shown below. The drop in the impedance magnitude below ~1MHz follows the expected shape of a capacitor. Past ~1MHz, the inductance starts rising again, following the expected shape of an inductor. The minimum point is the self-resonant frequency (SRF) where the capacitance and inductance reactances "cancel" and the impedance is driven by the series resistor. Since the impedance rises again past the self-resonant frequency, the effective capacitance is lower.

C3216X5R1V226M160AC impedance vs frequency

Let's consider a point past the SRF now:
C3216X5R1V226M160AC impedance highlighted at 8.684MHz

The cap is nominally 22uF. At 8.648MHz, the expected impedance would be given by:

Expected impedance would therefore be 0.84 mΩ. However, the chart indicates that the impedance is 56 mΩ. Based on that, the effective capacitance can be back-worked to be 0.33uF for this 22uF cap!

Now you could say that, this frequency is pretty high and way past the SRF so of course the cap isn't behaving as we expect it to. However, this ties directly to the electrolytic cap I was trying to use too.

When looking at the electrolytic part's datasheet, I noticed no equivalent SRF or impedance information. Electrolytic capacitors are known to have lower SRF than ceramic capacitors, but how bad is it actually?

As an aside, what causes the parasitic inductance and why is it better than the ceramic caps? A good reference to understand this is Improved Spice Models of Aluminum Electrolytic Capacitors for Inverter Applications 

In summary, consider the construction of a typical electrolytic capacitor where the contact foils are rolled within the package. The images below are taken from the paper linked above.
 

The current flow through the structure can be modelled as an RC ladder network with distributed resistances and capacitances. This translates to capacitances further down the ladder network (such as C5 shown below) have larger series resistances and the associated time constants are large compared to the period of the voltage across the cap. This results in a drop in capacitance with frequency, greater than that of just the contact and packaging inductances.

A side note of interest is that the opposing current directions through the foils can help cancel the parasitic inductances, asides from small mismatches in foil alignment, depending on device assembly.

Is there an easy way to verify this for the cap I have? And can I trust the 19uF reading from the LCR meter? That's why I proceeded to do. (The reason for the distrust was more due to the meter misbehaving in lab for other measurements but is good to check against.)

I have a Digilent Analog Discovery 2 at home, which I have found to be very handy! I recently learned I can use it as an impedance analyzer
Digilent Analog Discovery 2

The following is the required setup to get impedance measurements.
Impedance measurement setup: "Load" is the cap under test

Using this setup, I am now able to get some quick impedance measurements for my cap. A key aspect of this is to perform the short compensation to ensure that measurement parasitics are taken into account. Without performing this compensation at first, I saw very different results due to the ~50nH of additional parasitic inductance through my measurement setup.

The reactance measurement is shown below:
Reactance measurement from 1kHz to 1MHz

I exported the reactance measurements, and then found the values of C0 and L0. C0 is the capacitance at the lowest measurement frequency and L0 is the inductance at the highest measurement frequency. This allows me to simply model the capacitor as a constant C0 in series with constant L0 (and also a constant series resistor but that isn't factored into this reactance measurement).

For these measurements, the values of C0 and L0 are 407.6 uF and 34.5 nH. C0 is within 20% of the 470uF capacitance, as per the part's spec. Overlaying the reactance due to C0 and L0 on the measured reactances yields the following plot.
Parasitic L, C fit on reactance measurements

This shows that barring the area around the SRF, the reactance is very well modelled by the constant C0 and L0. Considering the reactance, then, the equivalent capacitance can be computed as shown below.
"Effective" capacitance fit on reactance measurements


At 100 kHz, the capacitance is about 80 uF and at 200 kHz, the capacitance is about 20 uF! That is a HUGE drop from the 470 uF rating of the part (and measured 408 uF at low frequency). The self resonant frequency is about 40 kHz, which is very low compared to the ceramic cap shown previously. Of course, this is a different part in a different larger package and so that is not a fair comparison.

Back to where I was trying to use this! This is the input cap for a buck converter operating in the 80-200 kHz range. With such a substantial drop in effective capacitance, the input current ripple will be substantially higher than that predicted/computed with a 408uF cap!

In this particular converter, the 408uF cap would lead to about 23 mVpp ripple. However, with a 20uF cap, this goes up to 463 mVpp. Interestingly, operating this converter at a slower 100 kHz with the same cap (80uF @ 100kHz) could result in a lower ripple!

Be careful which parts you use! And make sure you consider the frequency-dependent behavior! Once you're above the SRF, the capacitance value drops precipitously. If possible, operate below the SRF or make sure you understand what the impact will be if you don't. There's also the consideration of ESR but with electrolytic caps, that tends to decrease with resistance - which is why you'll see ripple current specs get better at higher frequencies for electrolytic caps.

Jan 2, 2024

Quick and dirty PIC16F72 programmer with the Pico


Accompanying Github repo: https://github.com/SyedTahmidMahbub/q-dpico_picprog72

Having come to Dhaka over winter break, I was able to scrounge through the 10+ year-old collection of electronics stuff my parents had in storage from when I would experiment with electronics during the initial days of this blog. Among the many parts, I stumbled upon a large number of PIC16F72 MCU's - the defacto 8-bit cheap MCU of choice for many (commercial) projects. However, I couldn't seem to find the corresponding PICKIT2/3 programmer from back then - or one of the clones I had made - within the storage cabinets. At the same time, I had been working on some projects with the Pi Pico (as mentioned in the blog previously: https://tahmidmc.blogspot.com/2023/08/2023-updates-phd-pi-pico.html). This seemed like the perfect use case for the Pico - a very quick and dirty programmer to flash the PIC16F72. With its 2MB onboard flash, a very easy-to-program Micropython interface and the PIC16F72's fairly timing insensitive ICSP protocol (http://ww1.microchip.com/downloads/en/devicedoc/39588a.pdf), I set out to build a programmer to flash some test code onto the PIC16F72. I made use of whatever parts I could scrounge from the parts bin to put the project together.

As expected, Micropython on the Pi Pico enabled a super-quick development time. To echo what I had previously quoted from the Raspberry Pi foundation:

Computing is just so cheap compared to what it has been historically. That then enables things that are maybe not super efficient, not super tight timing like Micropython but who cares at that point? A lot of people will come in and say things like 'in this benchmark, I found that MicroPython is 100x slower than C' but if your C code is 100x faster than you need, then it doesn't matter. You just write the code you need and you focus on the parts that add value to your project and then you move on to your next project.

And this is the perfect use case! It's not the highest performance result but it gets the job done and the project development was super quick!

The details for the PIC16F72 programming are covered in Microchip's documentation: http://ww1.microchip.com/downloads/en/devicedoc/39588a.pdf

A description of Microchip's HEX file format is provided here: https://microchipdeveloper.com/xwiki/bin/view/software-tools/ipe/sqtp-file-format-specification/intel-hex/

The hardware elements of the project have a few key aspects:

  1. A higher voltage power supply is required for programming. This is between 12.75V and 13.25V VPP. To achieve this, a boost converter is used to raise the 5V USB rail to about 13V. I didn't have any inductors on hand except one unmarked part I found, that measured around 1.8mH. The boost converter operates in discontinuous conduction mode with the minimal VPP required current. Because of the 3.3V IO level of the Pico, I used an NPN transistor instead of a logic level MOSFET I had on hand due to the MOSFET's relatively high threshold voltage.
  2. A VPP level shifter is required to drive the VPP pin up to 13V or hold it low. A PC817 optocoupler is used for this.
  3. Level shifters are not needed for the PGD and PGC programming lines since the 3.3V from the Pico is high enough (>2V) for the PIC to register, even though the PIC is powered off 5V.
One useful and interesting aspect of the project is that no separate programming interface is required to transfer the PIC's HEX file from the PC to the Pico. Since the PIC16F72's flash storage is so small compared to the Pico's onboard storage, and using the Micropython setup on the Pico exposes a filesystem, I can just copy the HEX file contents onto a file on the Pico using the Thonny editor. And then hit run in Thonny to program the PIC!

The software is effectively the following:
  1. Configure the IOs for their corresponding functions.
  2. Configure PWM for the boost converter, running at 50kHz.
    1. Adjust the duty cycle until the output is near 13.2V.
    2. The output voltage is sensed by an ADC channel.
  3. Hold this duty cycle for the output voltage - at this point, the feedback loop is stopped.
  4. Detect the target PIC.
  5. If detected, issue a bulk erase and then check that the part is blank.
  6. Upon success, flash the words read from the HEX file.
To modify for another similar (small) PIC, adjust the constants at the beginning of the code:
  • CODE_START_ADDR
  • CODE_END_ADDR
  • CONFIG_START_ADDR
  • CONFIG_END_ADDR
  • DEVID_PIC16F72
If you use a different inductor for the boost, you can play around with the switching frequency and loop time too.


The schematic for the setup is shown below:


The code can be found here on this github repo: https://github.com/SyedTahmidMahbub/q-dpico_picprog72

The repo also has 2 test hex files test.hex and testbig.hex where the latter has a large array in flash to program over a larger amount of the flash storage.

Shown below is an example output from Thonny when I set the target voltage to 13.15V and flashed the testbig.hex file:
The code and project are by no means optimized for speed or performance. They are, however, optimized for development time! The project could easily be adapted to support other MCUs, and to create an ultra-cheap programmer - something I had previously done with the PIC16F1459 but the Pico enables greater versatility. Due to the onboard stoarage, the Pico could also program a PIC with no interface to a computer for isolated industrial flashing settings.

Finally, a quick photo to truly highlight the quick and dirty build: