# Tahmid's blog

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I am currently a PhD student at UC Berkeley, following a 6-year journey working at Apple after my undergrad years at Cornell University. I grew up in Dhaka, Bangladesh where my interest in electronics was cultivated, resulting in the creation of this blog.

## Sizing IR2110 high-side bootstrap capacitor

I have previously discussed the IR2110 gate driver on this blog: https://tahmidmc.blogspot.com/2013/01/using-high-low-side-driver-ir2110-with.html

A crucial part of the high-side gate driver is the sizing of the bootstrap cap. A common sizing strategy is to "use a large cap" and use a larger one for small frequencies. Here, I present a simple method to model the discharge of the cap in a simple LTSpice simulation to inform the capacitor sizing. Shown below is the simulation setup along with the functional block diagram of the IR2110.

A few key points regarding the setup:
• S1 and S2 represent the high side gate drive FETs in the IR2110 that drive the HO pin.
• S3 and S4 represent the low side gate drive FETs in the IR2110 that drive the LO pin.
• Ibs represents the quiescent VBS current and the offset supply leakage current: Ibs = ILK + IQBS. From datasheet, that evaluates to a max of 50µA + 230µA = 280µA.
• GDH and GDL have their threshold voltages set at +0.5V (refH) and -0.5V (refL) respectively. These, along with yH and yL generate the drive pulses for S1-S4 and correspondingly M1-M2.
• C1 is the bootstrap cap here, specified at 1µF.
The logic for generating the drive signals for S1-S4 is shown in the diagrams below. Click on the images to expand.

Now, let's go on to the key discussion regarding the cap sizing.

Once the cap is charged, there are a few discharge paths:
• Charge transferred to the gate of the MOSFET being driven
• Current draw due to the gate-source resistor
• Leakage paths - the largest one modeled here is Ibs
For the charge transfer, consider the gate charge of the MOSFET being driven. This can be gathered from the datasheet of the MOSFET. For the IRFZ44N in this simulation, this is around 40nC-50nC as can be seen from Fig 6 in the IRFZ44N datasheet:
The voltage droop due to charging the MOSFET gate (Qg) can be estimated as:
The voltage droop due to driving current through the gate-source resistor can be estimated as:

VD1 is the forward drop for the bootstrap diode D1. Ton is the on-time given by the product of the duty cycle and period.

Below is the voltage across the boostrap cap from the sim:

Observations from this waveform:
• Between 440µs and 500µs, M2 is on, which charges the bootstrap cap C1 through D1. A larger charge resistance (D1 on-state resistance) or a larger bootstrap cap C1 would increase this charging time.
• At 500µs, M1 is turned on. Note that this simulation doesn't model the deadtime, but since we're primarily interested in the boostrap cap's dynamics, that is fine.
• The sharp vertical drop right after 500µs is the charge transfer to M1's gate.
• The continued droop afterwards, to 540µs, is due to Ibs and the gate-source-resistance.
• The voltage drops from 11.403V to 10.921V.
• VGS for M1 tracks this voltage from 500µs to 540µs.

Below is a simple script to estimate the total droop with Python:
import numpy as np

D = 0.4
Tperiod = 100e-6
Ton = D * Tperiod
V0 = 11.403

Cboostrap = 1e-6
Qg_FET = 45e-9
Rg_on = 1031
Ibs = 280e-6

dV_Qg = -Qg_FET/Cboostrap
dV_Rg = -V0 * (1 - np.exp(-Ton/Rg_on/Cboostrap))
dV_Ibs = -Ibs/Cboostrap * Ton

V_final = V0 + dV_Qg + dV_Rg + dV_Ibs
print("Droop sources:")
print(f" Gate charge: {dV_Qg :.3f} V")
print(f" Gate resistor: {dV_Rg :.3f} V")
print(f" Ibs: {dV_Ibs :.3f} V")

print(f"Droops from {V0 :.3f} V to {V_final :.3f} V")

The output of the script is:

Droop sources:
Gate charge: -0.045 V
Gate resistor: -0.434 V
Ibs: -0.011 V
Droops from 11.403 V to 10.913 V

The computed droop matches very well with the simulation!

Key observations:
• The droop will get worse with reduced gate-source resistance. Using a larger resistance than 1k will reduce the droop.
• The droop will get worse with a longer on-time. This is why a larger capacitance is needed when operating at lower frequencies such as 50Hz or 60Hz.
• Using a super large cap will increase how long the cap will require being charged at startup. This may be dealt with by precharging the cap (by turning on M2) before M1 has to be turned on.
• A 100% duty cycle can't be used since the bootstrap cap can't be recharged. How high the max possible duty cycle is depends on how long it takes to recharge the cap through the bootstrap diode.
• Gate charge for the MOSFET is a weak function of applied voltage and a very strong function of gate voltage. A larger gate drive voltage will result in a greater droop. Note though that this may not matter if the gate-source resistor dominates the droop.
• A good max allowable droop is given by the 9.7V figure for the IR2110's max VBS undervoltage threshold. Given that there are always additional leakage components, and the cap has an associated tolerance (in many cases >20%), you will want to build in lots of margin.

Hopefully, this was a useful introduction to sizing the bootstrap capacitance for the IR2110 (or other gate driver). Here is also a good reference to look at: AN-978

If you want further clarification on any aspect of this, do let me know in the comments!